A Parallel Image Computer with a Distributed Frame Buffer: System Architecture and Programming

Abstract

We describe the system architecture and the programming environment of the Pixel Machine - a parallel image computer for 2D and 3D image synthesis and analysis. The architecture of the computer is based on an array of asynchronous MIMD nodes with a parallel access to a large frame buffer. The system consists of a pipeline of pipe nodes which execute sequential algorithms and an array of m x n pixel nodes which execute parallel algorithms. A pixel node accesses every m-th pixel on every n-th scan line of a distributed frame buffer. Each processing node is based on a high-speed, floating-point programmable processor. The programmability of the computer allows all algorithms to be implemented in software. A set of mapping functions transfers image algorithms written for conventional single-processor computers to algorithms which execute in the pixel nodes and access the distributed frame buffer. The ability to use floating-point computations in pixel operations, such as antialiasing, ray tracing, and filtering, allows high-quality image generation and processing. The image computer provides up to 820 megaflops of peak processing power and 48 megabytes of memory for data-visualization applications.