A PIPELINED-PARALLEL ARCHITECTURE FOR 2.5-D BATCH RASTERIZERS

Abstract

The emergence of application programs that take advantage of highly expressive page description languages has sharply increased the amount of computing required for rasterizing an average page, and single-microprocessor rasterizers presently limit the performance of most printers. The pipelined-parallel architecture employs intrapage parallelism to permit the construction of cost-effective multiprocessor rasterizers for computer-driven high-function printers. Initially, blocks of datastream that are independent in terms of datastream environment are identified by a sequential “scanner“. They are then processed in parallel, and each is converted into a multitude of simple, regular objects, which are sorted by “geographical” target on the page into “bins” that correspond to a predetermined partition of the page. Sequencing information is retained. The bins are then processed in parallel (sequentially within each bin) to build the full-page bitmap. The phases are pipelined for increased performance. By breaking rasterization into two main stages and parallelizing along a different dimension in each of them, we are able to attain intrapage parallelism while maintaining correctness, even with non commutative merging modes, such as “overpaint”.